Profile

English Ver. (-> Japanese Ver.)

Research Interests

Reconfigurable Computing
- CGRA (Corase-Grained Reconfigurable Architecures)
- Power Optimization
Computer Archtecure
- 3-D stacked chip
- Heterogenus Computing
- High Efficient Accelarator

Biography

In Jan. 1995, he was born in Kanagawa Pref., Japan.

Education

In Mar. 2013, he graduated from Kanagawa Prefectural Chigasaki-Hokuryo High School.
In Mar. 2017, he received the B.E. degree from Keio university, Japan.
In Mar. 2019, he received the M.E degree from Keio univerisity, Japan.
In Mar. 2021, he received the Ph.D. degree from Keio univerisity, Japan. [Ph.D. Thesis]

Research Experience

From Apr. 2019 to Mar. 2021, JSPS Research Fellowship for Young Scientists (DC1).
In Oct. 2020, internship program at RIKEN Center for Computational Science.
From Dec. 2020 to Sep. 2021, part-time researcher at RIKEN Center for Computational Science.
From Apr. 2021 to Sep. 2021, JSPS Research Fellowship for Young Scientists (PD).
From Apr. 2021 to Sep. 2021, Research Fellow in Keio University, Japan.
From Nov. 2021 to Mar 2022, visiting researcher in RIKEN Center for Computational Science.
From Oct. 2021 to present, assistant professor in The University of Tokyo.
From Apr. 2022 to present, visiting research associate in Keio University.
From Oct. 2022 to present, JST PRESTO researcher (Concurrent post)

Work Experience

From Apr. 2017 to Mar. 2021, he is working as a teaching assistant at Keio University, Japan.
From Apr. 2017 to Mar. 2021, he is also working as a teaching assistant at Tokyo University of Technology, Japan.
From 2019 to 2021, he gave a lecture on “Computer Literacy” as a part-time lecturer at Junior College of Aizu, Japan.

Qualifications

Fundamental Information Technology Engineer Examination (2015)
Applied Information Technology Engineer Examination (2015)
Embedded Systems Specialist Examination (2016)

Scholarships

Repayment Exemption for Graduate Students with Excellent Achievements JASSO type-1 scholarship exemption of all of loan (2019)

Grants

From Apr. 2019 to Mar. 2022, JSPS KAKENHI Grant-in-Aid for JSPS Research Fellow (DC1), Grant number 19J21493: 2,500,000 JPY.
From Apr. 2022 to Mar. 2023, Tateishi Science and Technology Foundation Research Grant (A), 2,778,000 JPY.
From Apr. 2022 to Mar. 2025, JSPS KAKENHI Grant-in-Aid for Early-Career Scientists , Grant number 22K17866: 4,680,000 JPY.
From Jun. 2024 to Mar. 2025, Kioxia Corporation Encouragement Research, 2,200,000 JPY.
From Oct. 2022 to Mar. 2026, JST Strategic Basic Research Programs (PRESTO), Research area “Strengthening ICT Infrastructure for Social Change” JPMJPR22P5
From Feb. 2024 to Mar. 2027, JST Adopting Sustainable Partnerships for Innovative Research Ecosystem (ASPIRE), “Exploring adaptive data compression hardware for next-generation highly efficient computational infrastructure” (Co-PI)
From Feb. 2024 to Mar. 2027, JST Adopting Sustainable Partnerships for Innovative Research Ecosystem (ASPIRE), “Development of a coarse-grained logic array platform for ASIC design universalization” (Collaborating researcher)

Awards

IEICE RECONF Excellent Presentation Award (2023)
IPSJ SLDM special jury award (2023)
IPSJ SLDM Excellent Presentation Award (2023)
Funai Information Technology Award for Young Researchers (2023)
IEEE Computer Society Japan Chapter Young Author Award (2022)
IEICE CPSY Young Presentation Award (2022)
The 37th Telecom System Technology Student Award, Telecommunications Advancement Foundation (2022)
IEEE CEDA AJJC Design Gaia Best Poster Award (2019)
IEICE CPSY Young Presentation Award (2018)

For co-authors

Hisako Ito, xSIG 2024 Poster Award (2024)
Hisako Ito, IPSJ ARC Young Encouragement Award (2024)
Ai Nozaki, IPSJ Computer Science Research Award for Young Scientists (2024)
Ai Nozaki, IPSJ ARC Young Encouragement Award (2024)
Aika Kamei, IPSJ SLDM Excellent Presentation Award (2023)
Aika Kamei, IEEE CEDA AJJC Academic Research Award (2022)
Yosuke Yanai, IEICE CPSY Young Presentation Award (2022)
Aika Kamei, IPSJ Yamashita SIG Research Award (2022)
Aika Kamei, IPSJ SLDM Excellent Presentation Award (2022)
Aika Kamei, IPSJ SLDM Excellent Presentation Award (2021)
Aika Kamei, MCSoC 2021 Best Paper Award (2021)
Ayaka Ohwada, IEICE CPSY Young Presentation Award (2020)

Publications (selected)

The full list is here.

International Journals

Takuya Kojima, Hayate Okuhara, Masaaki Kondo, Hideharu Amano, “A Scalable Body Bias Optimization Method Towards Low-Power CGRAs”, IEEE Micro, Vol. 43, no. 1, pp. 49-57, Jan.-Feb. 2023. DOI: 10.1109/MM.2022.3226739. [IEEE Xplore]
Takuya Kojima, Ayaka Ohwada, Hideharu Amano, “Mapping-Aware Kernel Partitioning Method for CGRAs Assisted by Deep Learning”, IEEE Transactions on Parallel and Distributed Systems. DOI: 10.1109/TPDS.2021.3107746. [IEEE Xplore] (Telecom System Technology Student Award)
Takuya Kojima, Nguyen Anh Vu Doan, Hideharu Amano, “GenMap: A Genetic Algorithmic Approach for Optimizing Spatial Mapping of Coarse Grained Reconfigurable Architectures”, IEEE Transactions on Very Large Scale Integration Systems (VLSI), Vol. 28, no. 11, pp.2383-2396, Nov 2020. DOI: 10.1109/TVLSI.2020.3009225. [IEEE Xplore] [Tool available at Github]

International Conferences (Peer-reviewed)

Takeharu Ikezoe, Takuya Kojima, and Hideharu Amano, “A Coarse-Grained Reconfigurable Architecture with a Fault Tolerant Non-volatile Configurable Memory”, 2019 International Conference on Field-Programmable Technology (FPT),Tianjin, China, December, 2019.
Takuya Kojima, Naoki Ando, Yusuke Matsushita and Hideharu Amano, “Demonstration of Low Power Stream Processing Using a Variable Pipelined CGRA”, 29th International Conference on Field Programmable Logic and Applications (FPL), Barcelona, Spain, September, 2019. (Demo Paper) [Paper] [Poster]
Takuya Kojima and Hideharu Amano, “A Configuration Data Multicasting Method for Coarse-Grained Reconfigurable Architectures”, 28th International Conference on Field Programmable Logic and Applications (FPL), Dublin, Ireland, August, 2018. [Paper] [Poster]
Takuya Kojima, Naoki Ando, Yusuke Matsushita, Hayate Okuhara, Nguyen Anh Vu Doan and Hideharu Amano, “Real Chip Evaluation of a Low Power CGRA with Optimized Application Mapping”, International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2018), Canada, June, 2018. [Paper] [Slide]
Takuya Kojima, Naoki Ando, Hayate Okuhara, Hideharu Amano, “Glitch-aware Variable Pipeline Optimization for CGRAs”, ReConFig 2017, Mexico, December 2017. [Paper] [Poster]
Takuya Kojima, Naoki Ando, Hayate Okuhara, Ng. Anh Vu Doan, Hideharu Amano, “Body Bias Optimization for Variable Pipelined CGRA”, 27th International Conference on Field-Programmable Logic and Applications(FPL), Belgium, September 2017. [Paper] [Poster]

Japanese domestic conferences/Technical reports

Takuya Kojima, “A Performance Analysis of OpenMP GPU Offloading in LLVM”, HotSPA 2022, Yuzawa Toei Hotel, Niigata, Oct. 2022. (IEICE CPSY Young Presentation Award)
小島拓也, 天野英晴, “CGRAのためのアプリケーションマッピングフレームワークGenMapの実装と実機評価”, デザインガイア2019 -VLSI設計の新しい大地-, 愛媛県男女共同参画センター, 愛媛, 2019年11月. [Paper] (IEEE CEDA AJJC Design Gaia Best Poster Award)
Takuya Kojima, Naoki Ando, Yusuke Matsushita, Hayate Okuhara, Ng. Doan Anh Vu, Hideharu Amano, “Low Power Stream Processing on a Variable Pipelined Accelerator CCSOTB2”, Hida Area Local Industry Promotion Center, Takayama-shi, Nov. 2018. [Paper] (IEICE CPSY Young Presentation Award)

Acknowledgement

A part of our work is supported by a Grant-in-Aid for Scientific Research(S) Grant Number 25220002, a Grant-in-Aid for Scientific Research(B) Grant Number 18H03215, a Grant-in-Aid for JSPS Fellows Grant Number 19J21493 and JST CREST Grant Number JPMJCR19K1. Also, A part of our work is supported by VLSI Design and Education Center(VDEC), the University of Tokyo in collaboration with Synopsys, Inc. and Cadence Design Systems, Inc.