Takuya Kojima

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Nakamura-Takase Laboratory, Graduate School of Information Science and Technology, The University of Tokyo

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Publications

English Ver. (-> Japanese Ver.)

International Journals

  1. Souhei Takagi, Takuya Kojima, Hideharu Amano, Morihiro Kuga, Masahiro Iida, “Applying Run-Length Compression to the Configuration Data of SLM Fine-Grained Reconfigurable Logic”, IEICE Transaction on Information and Systems. DOI: 10.1587/transinf.2024EDP7033

  2. Aika Kamei , Hideharu Amano, Takuya Kojima, Daiki Yokoyama, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, Kazuhiro Bessho, “A Variation-Aware MTJ Store Energy Estimation Model for Edge Devices With Verify-and-Retryable Nonvolatile Flip-Flops”, IEEE Transactions on Very Large Scale Integration Systems (VLSI), Vol. 31, no. 4, pp.532-542, April 2023. DOI: 10.1109/TVLSI.2023.3237794 [IEEE Xplore]

  3. Takuya Kojima, Hayate Okuhara, Masaaki Kondo, Hideharu Amano, “A Scalable Body Bias Optimization Method Towards Low-Power CGRAs”, IEEE Micro, Vol. 43, no. 1, pp. 49-57, Jan.-Feb. 2023. DOI: 10.1109/MM.2022.3226739. [IEEE Xplore]

  4. Takuya Kojima, Ayaka Ohwada, Hideharu Amano, “Mapping-Aware Kernel Partitioning Method for CGRAs Assisted by Deep Learning”, IEEE Transactions on Parallel and Distributed Systems, Vol. 33, no. 5, pp.1213-1230, May 2022. DOI: 10.1109/TPDS.2021.3107746. [IEEE Xplore] (Telecom System Technology Student Award)

  5. Takeharu Ikezoe, Takuya Kojima, Hideharu Amano, “Recovering faulty Non-volatile Flip Flops for Coarse-Grained Reconfigurable Architectures”, IEICE Transactions on Electronics, Vol.E104-C, No.6, pp.215-225, Jun. 2021. DOI: 10.1587/transele.2020LHP0002.

  6. Takuya Kojima, Nguyen Anh Vu Doan, Hideharu Amano, “GenMap: A Genetic Algorithmic Approach for Optimizing Spatial Mapping of Coarse Grained Reconfigurable Architectures”, IEEE Transactions on Very Large Scale Integration Systems (VLSI), Vol. 28, no. 11, pp.2383-2396, Nov 2020. DOI: 10.1109/TVLSI.2020.3009225. [IEEE Xplore] [Tool available at Github]

  7. Takuya Kojima, and Hideharu Amano, “A Fine-Grained Multicasting of Configuration data for Coarse-Grained Reconfigurable Architectures”, IEICE Transactions on Information and Systems, Vol.E102-D,No.7,pp.1247-1256,Jul. 2019. DOI:10.1587/transinf.2018EDP7336. [Paper]

  8. Takuya Kojima, Naoki Ando, Hayate Okuhara, Ng. Anh Vu Doan and Hideharu Amano, “Optimization of Body Biasing for Variable Pipelined Coarse-Grained Reconfigurable Architectures”, IEICE Transactions on Information and Systems, Vol.E101-D, No.6, pp.1532-1540, Jun 2018. DOI: 10.1587/transinf.2017EDP7308. [Paper]

Domestic Journals (In Japanese)

  1. Takuya Kojima, Takeharu Ikezoe, Hideharu Amano, “CubeSim: A Cycle Accurate Simulator for Multicore System with 3D SiP”, IEICE Transactions on Information and Systems, Vol.J104-D, No.04, pp.228-241, Apr. 2021. DOI: 10.14923/transinfj.2020PDP0046. [Paper] [English abstract]

International Conferences (Peer-reviewed)

  1. Ai Nozaki, Takuya Kojima, Hiroshi Nakamura, Hideki Takase, “MLIR-based Homomorphic Encryption Compiler for GPUs”, International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2024), Porto, Portugal, June, 2024.

  2. Makoto Saito, Takuya Kojima, Hideki Takase, Hiroshi Nakamura, “A Scalable Mapping Method for Elastic CGRAs”, 2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), San Francisco, USA, May, 2024.

  3. Takuya Kojima, Yosuke Yanai, Hayate Okuhara, Hideharu Amano, Morihiro Kuga, Masahiro Iida, “SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks”, COOLCHIPS27, Japan, April, 2024.

  4. Makoto Saito, Takuya Kojima, Hideki Takase, Hiroshi Nakamura, “A Data-Flow Visualization for CGRA Debugging”, ASPIRE 2024 HIROSHIMA (International workshop in conjunction with the IEICE General Conference), Hiroshima, Japan, Mar. 2024.

  5. Hajime Takishita, Takuya Kojima, Hideharu Amano , “CGRA architecture generation for implementing a systolic array”, ASPIRE 2024 HIROSHIMA (International workshop in conjunction with the IEICE General Conference), Hiroshima, Japan, Mar. 2024.

  6. Kaito Kutsuna, Takuya Kojima, Hideki Takase, Hiroshi Nakamura, “An Area-Efficient Coarse-Grained Reconfigurable Array Design for Approximate Computing”, 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2023), Singapore, December, 2023.

  7. Makoto Saito, Takuya Kojima, Hideki Takase, Hiroshi Nakamura, ”ILP based Mapping for Elastic CGRAs”, The 29th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications(RTCSA 23), Niigata, Japan, Aug. 2023.

  8. Boma Adhi, Carlos Cortes, Emanuele Del Sozzo, Tomohiro Ueno, Yiyu Tan, Takuya Kojima, Artur Podobas, Kentaro Sano, “Less for More: Reducing Intra-CGRA Connectivity for Higher Performance and Efficiency in HPC”, 2023 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW),　Florida, USA, May 2023.

  9. Boma Adhi, Carlos Cortes, Tomohiro Ueno, Yiyu Tan, Takuya Kojima, Artur Podobas, Kentaro Sano, “Exploring Inter-tile connectivity for HPC-oriented CGRA with Lower Resource Usage”, 2022 International Conference on Field-Programmable Technology (FPT), Hong Kong, China, December, 2022.

  10. Boma Adhi, Carlos Cortes, Yiyu Tan, Takuya Kojima, Artur Podobas, Kentaro Sano, “The Cost of Flexibility: Embedded versus Discrete Routers in CGRAs for HPC”, 2022 IEEE International Conference on Cluster Computing (CLUSTER), Germany, Sep. 2022.

  11. Takuya Kojima, Boma Adhi, Carlos Cortes, Yiyu Tan, Kentaro Sano, “An Architecture-Independent CGRA Compiler enabling OpenMP Applications”, 2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), virtual, May 2022. [Paper] [Slide] [Tool available at Github]

  12. Boma Adhi, Carlos Cortes, Yiyu Tan, Takuya Kojima, Artur Podobas, Kentaro Sano, “Exploration Framework for Synthesizable CGRAs Targeting HPC: Initial Design and Evaluation”, 2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), virtual, May 2022.

  13. Takuya Kojima, Hayate Okuhara, Masaaki Kondo, Hideharu Amano, “Body Bias Control on a CGRA based on Convex Optimization”, COOLCHIPS25, Japan, April, 2022. [Paper] [Slide]

  14. Ayaka Ohwada, Takuya Kojima, Hideharu Amano, “An efficient compilation of coarse-grained reconfigurable architectures utilizing pre-optimized sub-graph mappings”, 30th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP 2022).

  15. Boma Adhi, Carlos Cortes, Yiyu Tan, Takuya Kojima, Artur Podobas, Kentaro Sano, “RIKEN CGRA: Reconfigurable Data-Driven Architecture for Future HPC” (Poster), The International Conference on High Performance Computing in Asia-Pacific Region (HPC Asia 2022), Japan, January, 2022.

  16. Aika Kamei , Takuya Kojima, Hideharu Amano, Daiki Yokoyama, Hisato Miyauchi, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, Kazuhiro Bessho, “Energy Saving in a Multi-Context Coarse Grained Reconfigurable Array with Non-Volatile Flip-Flops “, 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2021), Singapore, December, 2021. (Best Ppaper Award)

  17. Boma Adhi, Takuya Kojima, Yiyu Tan, Artur Podobas, Kentaro Sano, “RIKEN CGRA: Data-Driven Architecture as an Extension of Multicore CPU for Future HPC” (Research Poster), SC21: International Conference for High Performance Computing, Networking, Storage and Analysis, America, November, 2021.

  18. Ayaka Ohwada, Takuya Kojima, Hideharu Amano, “MENTAI: A Fully Automated CGRA Application Development Environment that Supports Hardware/Software Co-design”, Synthesis And System Integration of Mixed Information technologies (SASIMI2021), Japan, March, 2021.

  19. Ayaka Ohwada, Takuya Kojima, Hideharu Amano, “Compiler Framework for Spatial Mapping CGRA using LLVM”, COOLCHIPS23, Japan, April, 2020.

  20. Takeharu Ikezoe, Takuya Kojima, and Hideharu Amano, “A Coarse-Grained Reconfigurable Architecture with a Fault Tolerant Non-volatile Configurable Memory”, 2019 International Conference on Field-Programmable Technology (FPT),Tianjin, China, December, 2019.

  21. Hideto Kayashima , Takuya Kojima, Hayate Okuhara, Tsunaaki Shidei, Hideharu Amano, “Real Chip Performance Evaluation on Through Chip Interface IP for Renesas SOTB 65nm Process”, 7th International Symposium on Computing and Networking Workshops (CANDARW’19), Nagasaki, Japan, November, 2019.

  22. Ryohei Tomura, Takuya Kojima, and Hideharu Amano, “A Real chip evaluation of a CNN accelerator SNACC”, Synthesis And System Integration of Mixed Information technologies(SASIMI2019), Tainan, Taiwan, October, 2019.

  23. Sayaka Terashima, Takuya Kojima, Hayate Okuhara, Kazusa Musha, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo and Mitaro Namiki, “A Preliminary Evaluation of Building Block Computing Systems”, 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2019), Singapore, October, 2019. [Paper] [Slide]

  24. Takuya Kojima, Naoki Ando, Yusuke Matsushita and Hideharu Amano, “Demonstration of Low Power Stream Processing Using a Variable Pipelined CGRA”, 29th International Conference on Field Programmable Logic and Applications (FPL), Barcelona, Spain, September, 2019. (Demo Paper) [Paper] [Poster]

  25. Takuya Kojima and Hideharu Amano, “Refinements in Data Manipulation Method for Coarse Grained Reconfigurable Architectures”, 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2019), York, United Kingdom , July, 2019. [Paper] [Slide]

  26. Hideto Kayashima, Takuya Kojima, Hayate Okuhara, Tsunaaki Shidei and Hideharu Amano, “Real Chip Performance Evaluation of Inductive Coupling TCI IP”, COOLCHIPS22, Japan, April, 2019.

  27. Takuya Kojima and Hideharu Amano, “A Configuration Data Multicasting Method for Coarse-Grained Reconfigurable Architectures”, 28th International Conference on Field Programmable Logic and Applications (FPL), Dublin, Ireland, August, 2018. [Paper] [Poster]

  28. Takuya Kojima, Naoki Ando, Yusuke Matsushita, Hayate Okuhara, Nguyen Anh Vu Doan and Hideharu Amano, “Real Chip Evaluation of a Low Power CGRA with Optimized Application Mapping”, International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2018), Canada, June, 2018. [Paper] [Slide]

  29. Takeharu Ikezoe, Takuya Kojima, Hideharu Amano, Junya Akaike, Kimiyoshi Usami, Keizo Hiraga, Yusuke Shuto and Kojiro Yagami, “A micro-controller for MTJ-based Non-volatile Flip-flops for data verification”, COOLCHIPS21, Japan, April, 2018.

  30. Sayaka Terashima, Takuya Kojima, Hayate Okuhara, Yusuke Matsushita, Naoki Ando, Mitaro Namiki and Hideharu Amano, “A shared memory chip for twin-tower of chips”, Synthesis And System Integration of Mixed Information technologies(SASIMI2018), KUNIBIKI MESSE, March 2018.

  31. Takuya Kojima, Naoki Ando, Hayate Okuhara, Hideharu Amano, “Glitch-aware Variable Pipeline Optimization for CGRAs”, ReConFig 2017, Mexico, December 2017. [Paper] [Poster]

  32. Ryuichi Sakamoto, Ryo Takata, Jun Ishii, Masaaki Kondo, Hiroshi Nakamura, Tetsui Ohkubo, Takuya Kojima and Hideharu Amano, “Scalable Deep Neural Network Accelerator Cores with Cubic Integration using Through Chip Interface”, 2017 International SoC Design Conference (ISOCC 2017), Seoul, Korea, November, 2017.

  33. Ryuichi Sakamoto, Ryo Takata, Jun Ishii, Masaaki Kondo, Hiroshi Nakamura , Tetsui Ohkubo, Takuya Kojima and Hideharu Amano, “The Design and Implementation of Scalable Deep Neural Network Accelerator Cores”, MCSoC-17, Korea, September 2017.

  34. Takuya Kojima, Naoki Ando, Hayate Okuhara, Ng. Anh Vu Doan, Hideharu Amano, “Body Bias Optimization for Variable Pipelined CGRA”, 27th International Conference on Field-Programmable Logic and Applications(FPL), Belgium, September 2017. [Paper] [Poster]

  35. Takuya Kojima, Naoki Ando, Hayate Okuhara, Ng. Anh Vu Doan, Hideharu Amano, “Power Optimization for CGRA with Control of Variable Pipeline and Body Bias Voltage”, COOLCHIPS20, Japan, April 2017.

Japanese domestic conferences/Technical reports

  1. Ai Nozaki, Takuya Kojima, Hideki Takase, Hiroshi Nakamura, “Exploring AMD AI Engine for Accelerating Number Theoretic Transform”, SWoPP 2024, Awagin Hall, Tokushima, Aug. 2024.

  2. Haruto Ishii, Takuya Kojima, Hideki Takase, Hiroshi Nakamura, “Power-analysis side channel attack with auto encoder”, Security Summer Summit 2024, Sapporo Convention Center, Hokkaido, July 2024.

  3. Takuya Kojima, “A Framework for Efficient Evaluation of Side-Channel Attack Resistance”, HotSPA 2024, Isawa View Hotel, Yamanashi, June 2024. [Paper] [Slide]

  4. Hisako Ito, Takuya Kojima, Hideki Takase, Hiroshi Nakamura, “Study of control flow decoupling for controller design exploration in CGRA”, HotSPA 2024, Isawa View Hotel, Yamanashi, June 2024. (IPSJ ARC Young Encouragement Award)

  5. Ai Nozaki, Takuya Kojima, Hideki Takase, Hiroshi Nakamura, “A Homomorphic Encryption Compiler for GPUs using MLIR”, ETNET 2024, Iki no Shima Hall, Nagasaki, Mar. 2024. (IPSJ ARC Young Encouragement Award, IPSJ Computer Science Research Award for Young Scientists)

  6. Makoto Saito, Takuya Kojima, Hideki Takase, Hiroshi Nakamura, “”, Technical Report (VLD), Okinawa Gender Equality Center, Okinara, Feb. 2024.

  7. Hajime Takishita, Takuya Kojima, Hideharu Amano, “Design space exploration for a CGRA architecture that efficiently handles the Systolic algorithm”, Technical Report (RECONF), AIRBIC, Kanagawa, Jan. 2024.

  8. Souhei Takagi, Takuya Kojima, Hideharu Amano, Morihiro Kuga, Masahiro Iida, “Configuration Data Compression for SLM Fine-grained Reconfigurable Logic”, Design Gaia 2023 -New Field of VLSI Design-, Civic Auditorium Sears Home Yume Hall, Kumamoto, Nov. 2023.

  9. Takuya Kojima, Yosuke Yanai, Hayate Okuhara, Hideharu Amano, Morihiro Kuga, Masahiro Iida, “Library Development for RISC-V FPGA SoCs”, Technical Report (RECONF), Tokyo University of Agriculture and Technology Koganei campus, Tokyo, Sep. 2023. [Paper] [Slide]　 (IEICE RECONF Excellent Presentation Award)

  10. Makoto Saito, Takuya Kojima, Hideki Takase, Hiroshi Nakamura, “Construction of Visualization Environment for CGRA Operation Verification “, Technical Report (RECONF), Technical Report (RECONF), Tokyo University of Agriculture and Technology Koganei campus, Tokyo, Sep. 2023.

  11. Aika Kamei, Hideharu Amano, Takuya Kojima, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, Kazuhiro Bessho, “Energy minimization for Intermittent Operation Using an Energy Model of nonvolatile FF”, DA Symposium, Yunokuni Tensyo, Ishikawa, Sep. 2023. (IPSJ SLDM Excellent Presentation Award)

  12. Yosuke Yanai, Takuya Kojima, Hayate Okuhara, Masahiro Iida, Hideharu Amano, “Preliminary evaluation of “Power Evaluation of “SLMLET” chip with RISC-V MPU and SLM reconfigurable logic”, SWoPP 2023, Hakodate Arena, Hokkaido, Aug. 2023.

  13. Hideto Kayashima, Aika Kamei, Takuya Kojima, Hideharu Amano, “Consideration of Bus Arbitration Method for Inductive Coupling Wireless Communication Interface”, SWoPP 2023, Hakodate Arena, Hokkaido, Aug. 2023.

  14. Makoto Saito, Takuya Kojima, Hideki Takase, Hiroshi Nakamura, “Study on mapping methods for Elastic CGRA”, Technical Report (RECONF), Eikokuji Campus, Kochi University of Technology, Kochi, Jun. 2023.

  15. Takuya Kojima, Aika Kamei, Yosuke Yanai, Hideharu Amano, Morihiro Kuga, Masahiro Iida, “A Chip Testing Methodology for RISC-V SoC Using Jupyter Notebook”, ETNET 2023, Amagi town disaster prevention center, Kagoshima, Mar. 2023. [Paper] [Slide] [Demo video (in Japanese)] (IPSJ SLDM Excellent Presentation Award)

  16. Kaito Kutsuna, Takuya Kojima, Hideki Takase, Hiroshi Nakamura, “近似演算器を用いたCGRAとアプリケーションマッピングの協調設計”, Technical Report (VLD), Okinawaken Seinenkaikan, Okinawa, Mar. 2023.

  17. Carlos Cortes, Boma Adhi, Tomohiro Ueno, Yiyu Tan, Takuya Kojima, Artur Podobas, Kentaro Sano, “Evaluation of reduced routing resources for HPC-Oriented CGRAs”, Technical Report (RECONF), Hiyoshi Campus, Keio University, Yokohama, Jan, 2023.

  18. Takuya Kojima, Makoto Saito, Hiroshi Nakamura, “A Study of a Design Methodology for Various CGRA based on Diplomacy”, Design Gaia 2022 -New Field of VLSI Design-, Kanazawa Bunka Hall, Ishikawa, Nov. 2022. [Paper] [Slide]

  19. Takuya Kojima, “A Performance Analysis of OpenMP GPU Offloading in LLVM”, HotSPA 2022, Yuzawa Toei Hotel, Niigata, Oct. 2022. [Paper] [Slide] (IEICE CPSY Young Presentation Award)

  20. 小島拓也, 國分海渡, 齋藤　真, 富田祐永, 前田志温, “PYNQ-Z2を用いたハイブリッド型学生実験の実現”, RECONF研究会, emCAMPUS STUDIO(豊橋), 愛知, 2022年9月.

  21. Yosuke Yanai, Takuya Kojima, Hayate Okuhara, Masahiro Iida, Hideharu Amano, “Preliminary evaluation of “SLMLET” chip with RISC-V MP and SLM reconfigurable logic”, SWoPP 2022, Kaikyo Messe Shimonoseki, Yamaguchi, Jul. 2022.

  22. Aika Kamei, Takuya Kojima, Hideharu Amano, Daiki Yokoyama, Hisato Miyauchi, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, Kazuhiro Bessho, “A Variation-Aware MTJ Store Energy Estimation Model for Design Exploration of CGRA with Nonvolatile Flip-Flops”, ETNET 2022, Online, Mar. 2022. (IPSJ SLDM Excellent Presentation Award, IPSJ Yamashita SIG Research Award, IEEE CEDA AJJC Academic Research Award)

  23. Masato Nakagawa, Takuya Kojima, Hideki Takase, Hiroshi Nakamura, “GA-based Software Pipeline Scheduling for CGRAs”, Technical Report (CPSY), Online, Mar. 2022.

  24. Takuya Kojima, Carlos Cesar Cortes Torres, Boma Adhi, Yiyu Tan, Kentaro Sano, “A Preliminary Evaluation of a Compiler for RIKEN CGRA in HPC”, Technical Report (RECONF), Online, Jan. 2022. [Paper] [Slide]

  25. Boma Adhi, Carlos Cortes, Yiyu Tan, Takuya Kojima, Artur Podobas, Kentaro Sano, “Initial Design and Evaluation of RIKEN CGRA: Data-Driven Architecture for Future HPC”, Technical Report (RECONF), Online, Jan. 2022.

  26. Aika Kamei, Takuya Kojima, Hideharu Amano, Daiki Yokoyama, Hisato Miyauchi, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, “Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops”, Design Gaia 2021 -New Field of VLSI Design-, Online, Dec. 2021. (IPSJ SLDM Excellent Presentation Award)

  27. 小島拓也, 大和田彩夏, 天野英晴, “深層学習を用いたCGRAの効率的なアプリケーションマッピング手法”, SWoPP 2020, オンライン開催, 2020年7月. [Paper]

  28. Ayaka Ohwada, Takuya Kojima, Hideharu Amano, “Proposal for an IP-based Design Environment for CGRA Applications “, SWoPP 2020, Online, Jul. 2020.

  29. 小島拓也, 池添赳治, 天野英晴, “3次元積層型ヘテロジニアスプロセッサのためのシミュレータ開発とその応用”, ETNET 2020, 与論町中央公民館, 鹿児島, 2020年2月. [Paper][Slide]

  30. Ayaka Ohwada, Takuya Kojima, Hideharu Amano, “Construction and Evaluation of Software Development Environment for CGRA using LLVM “, ETNET 2020, Yoron-cho Chuou-Kouminkan, Kagoshima, Feb. 2020.

  31. 小島拓也, 天野英晴, “CGRAのためのアプリケーションマッピングフレームワークGenMapの実装と実機評価”, デザインガイア2019 -VLSI設計の新しい大地-, 愛媛県男女共同参画センター, 愛媛, 2019年11月. [Paper] (IEEE CEDA AJJC Design Gaia Best Poster Award)

  32. Hideto Kayashima , Takuya Kojima, Hayate Okuhara, Tsunaaki Shidei, Hideharu Amano, “Evaluation of Inter-chip Inductive Coupling Wireless Communication Technology”, Design Gaia 2019 -New Field of VLSI Design-, Ehime Prefecture Gender Equality Center, Matshuyama-shi, Nov. 2019.

  33. 戸村遼平, 小島拓也, 天野英晴, 坂本龍一, 近藤正章, “CNNアクセラレータSNACCの実チップ評価”, デザインガイア2019 -VLSI設計の新しい大地-, 愛媛県男女共同参画センター, 愛媛, 2019年11月.

  34. 池添赳治, 小島拓也, 天野英晴 “不揮発性構成メモリを用いた耐故障性粗粒度再構成可能アーキテクチャ”, RECONF研究会, 北九州国際会議場, 福岡, 2019年9月.

  35. 小島拓也, 天野英晴, “粗粒度再構成可能アーキテクチャCMAにおけるメモリバンクアクセスの改良”, SWoPP2019, 北見市民会館, 北海道, 2019年7月. [Paper]

  36. 天野英晴, 茅島秀人, 小島拓也, 坂本龍一, 近藤正章, 並木美太郎, “ビルディングブロック型積層システムの性能評価”, SWoPP2019, 北見市民会館, 北海道, 2019年7月.

  37. Hideharu Amano, Hideto Kayashima,Tsunaaki Shidei, Takuya Kojima, “The real chip evaluation of Through Chip Interface IP for Renesas 65nm SOTB process”, Technical reports on IEICE-VLD, Ookayama Campus, Tokyo Institute of Technology, Tokyo, May. 2019.

  38. 小島拓也, 天野英晴, “3次元積層型CGRAのためのアプリケーション割り当て手法の検討”, 学生・若手研究会, ホテルアトールエメラルド宮古島, 沖縄, 2018年12月.

  39. 寺嶋爽花, 小島拓也, 武者千嵯, 奥原颯, 天野英晴, “ツインタワー型共有メモリチップを用いたCNNアプリケーションの高速化”, 学生・若手研究会, ホテルアトールエメラルド宮古島, 沖縄, 2018年12月.

  40. Hideto Kayashima , Takuya Kojima, Hayate Okuhara, Hideharu Amano, “Real Chip Implementation of a verification scheme for an Inductive-Coupling ThruChip Interface”, Design Gaia 2018 -New Field of VLSI Design- , Satellite Campus Hiroshima, Hiroshima-shi, Dec. 2018.

  41. Takuya Kojima, Naoki Ando, Yusuke Matsushita, Hayate Okuhara, Ng. Doan Anh Vu, Hideharu Amano, “Low Power Stream Processing on a Variable Pipelined Accelerator CCSOTB2”, Hida Area Local Industry Promotion Center, Takayama-shi, Nov. 2018. [Paper] (CPSY Young Presentation Award)

  42. 小島拓也，安藤尚樹, 松下悠亮, 奥原　颯, Nguyen Anh Vu Doan, 天野英晴, “多目的遺伝的アルゴリズムを用いたCGRAマッピング最適化手法と実チップ評価”, RECONF研究会, LINE Fukuokaカフェスペース, 福岡, 2018年9月. [Paper]

  43. 小島拓也，安藤尚輝，天野英晴, “可変構造パイプラインを持つ粗粒度再構成アクセラレータCCSOTB2”, 第80回情報処理学会全国大会, 早稲田大学, 東京, 2018年3月. [Paper]

  44. 寺嶋爽花，小島拓也，奥原 颯，松下悠亮，安藤尚輝，並木美太郎，天野英晴, “ツインタワーのためのメモリチップ”, 第80回情報処理学会全国大会, 早稲田大学, 東京, 2018年3月.

  45. 松下悠亮，小島拓也，門本淳一郎，黒田忠広，天野英晴, マルチコア積層システムCube-2の実装と評価, 第80回情報処理学会全国大会, 早稲田大学, 東京, 2018年3月.

  46. 坂本龍一，高田 遼，石井 潤，近藤正章，中村 宏，大久保徹以，小島拓也，天野英晴 “TCIを用いた3次元積層型DNN向けアクセラレータSNACCの設計と評価”, 第80回情報処理学会全国大会, 早稲田大学, 東京, 2018年3月.

  47. 小島拓也,安藤尚輝,奥原 颯,天野 英晴,”グリッチを考慮したCGRAの可変パイプライン最適化”, デザインガイア2017 -VLSI設計の新しい大地-, くまもと県民交流館パレア, 熊本, 2017年11月. [Paper] [Poster]

  48. 安藤尚輝,小島拓也,天野英晴,”可変パイプラインCGRAの実チップ評価”, デザインガイア2017 -VLSI設計の新しい大地-, くまもと県民交流館パレア, 熊本, 2017年11月.

  49. 寺嶋爽花,小島拓也,奥原 颯,松下悠亮,安藤尚輝,並木美太郎,天野英晴,”ツインタワー用共有メモリチップの開発”, デザインガイア2017 -VLSI設計の新しい大地-, くまもと県民交流館パレア, 熊本, 2017年11月.

  50. 小島拓也, 安藤尚輝, 奥原颯, Anh Vu Doan, 天野英晴, “整数計画問題を用いたパイプライン型CGRAのボディバイアス電圧最適化”, HotSPA2017, 登別温泉第一滝本館, 北海道, 2017年5月. [Paper]

  51. 高田遼，石井潤，坂本龍一，近藤正章，中村宏，大久保徹以，小島拓也，天野英晴, “ディープニューラルネットワーク向けアクセラレータチップの設計と性能評価”, cross-disciplinary Workshop on Computing Systems, Infrastructures, and Programming（xSIG）, 虎ノ門ヒルズフォーラム, 東京, 2017年4月.

  52. 小島拓也, 安藤尚輝, 松下悠亮, 奥原颯, 天野英晴, “パイプライン段数とボディバイアス電圧制御によるパイプライン型CGRAの電力削減手法の検討”, 具志川農村環境改善センター, 沖縄, 2017年3月. [Paper]

  53. 大久保徹以, 小島拓也, 天野英晴, 高田遼, 石井潤, 坂本龍一, 近藤正章, 中村宏, “無線3次元積層チップを用いたDeep Learningアクセラレータのコンパイラツールチェーン”, 具志川農村環境改善センター, 沖縄, 2017年3月.

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